When a semiconductor device fails electrically, one of the earliest questions is whether the damage came from electrostatic discharge or from electrical overstress. The two are routinely conflated in field reports, but they are different events with different signatures — and, more importantly for anyone with commercial exposure, different owners.
Two events, two energy regimes
Electrostatic discharge is very short and very high voltage, but carries little energy. A human-body-model event lasts on the order of nanoseconds. The damage it produces is correspondingly small and localised: punctured gate oxides, fused thin metallisation, damage at the specific structure that happened to be in the discharge path. It can be invisible at low magnification and, critically, can leave a device that still functions.
Electrical overstress delivers more energy over a longer interval — microseconds to seconds — and leaves gross thermal evidence. Melted bond wires, vaporised metal traces, cratered silicon, discoloured or ruptured packages. EOS damage is generally obvious once the package is opened; the analytical work lies in determining what circuit condition produced it.
The field maintains a dedicated body of work on exactly this boundary; the annual EOS/ESD Symposium proceedings are the standard reference (EOS/ESD 2018), and a published history of the symposia traces how the distinction has been formalised over four decades (EOS/ESD 2015).
The latent defect problem
The reason ESD attribution matters commercially is latency. An ESD event can weaken a gate oxide without causing immediate failure. The device passes final test, passes incoming inspection, is assembled into a product, and fails weeks or months into service as the damaged oxide degrades under normal operating stress. From the field, this looks like an early-life reliability problem with the finished product. From the physical evidence, it is a handling event that occurred somewhere upstream — at the component manufacturer, in transit, at a contract assembler, or on the customer line.
Susceptibility varies enormously by device technology, which is why device-specific characterisation work exists — for example, ESD failure-voltage studies on tunneling magnetoresistive heads at drive level (EOS/ESD 2007).
How the determination is made
The sequence is dictated by the fact that some evidence does not survive opening the package. Fault isolation comes first — thermal emission microscopy, lock-in thermography, and curve tracing to localise the defect electrically while the device is intact. Non-destructive imaging follows: X-ray and acoustic microscopy to find cracks, voids, and delamination inside the package. Only then is the device decapsulated, chemically or by laser, for optical and SEM inspection of metallisation and bond wires. Where the failing structure lies deeper, delayering or cross-sectioning reaches it.
At that point the morphology is usually decisive. Small, localised oxide puncture with minimal collateral thermal damage points to ESD. Extensive melting along a current path points to EOS. Mixed signatures are common and informative — an EOS event triggered by a circuit condition that a prior ESD-damaged structure created.
What it decides
The distinction rarely stays academic. ESD attribution points toward handling and process control, implicating manufacturing and logistics practices and the adequacy of ESD protection programmes. EOS attribution points toward the circuit — supply transients, inadequate protection design, a fault condition elsewhere in the system, or an application outside the device rating. In a supplier dispute, in a recall decision, or in litigation over a safety-critical system, those are very different conclusions.
One practical instruction outweighs the rest: do not power up a failed board again. Re-energising frequently destroys the original defect signature or superimposes new damage on it. Quarantine failed units with their date codes, lot traceability, and any stored error logs.
For the full mechanism set and examination protocol, see our specialization area on PCB and semiconductor failure analysis.