When a board or a device fails, the cause is often smaller than a human hair — and still decisive for a recall, a supplier dispute, or a lawsuit.
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Board and semiconductor failure analysis is a discipline of successive narrowing: from a system that misbehaves, to a board, to a net, to a device, and finally to a defect that may be a few micrometres across. The reason it works is that failure mechanisms leave characteristic signatures at every scale. Electrical overstress melts metallization in patterns distinct from electrostatic discharge damage; conductive anodic filamentation follows glass fibre bundles through the laminate; die cracks propagate along crystallographic planes. Getting to those signatures depends on doing fault isolation before decapsulation — once the package is opened, some evidence cannot be recovered.
Board-level and die-level mechanisms are distinct, and separating them early determines where the investigation goes next.
Electrostatic discharge puncturing gate oxides or fusing thin metallization — often latent, appearing as an early-life field failure.
Current or voltage beyond ratings melting bond wires and metallization, usually with visible thermal signatures.
Copper migrating along glass-fibre bundles under humidity and bias, creating shorts inside the laminate itself.
Thermal, mechanical, or moisture-driven cracking — including popcorning of moisture-sensitive packages during reflow.
Ionic residues, flux, and moisture driving electrochemical migration and dendritic growth between conductors.
Electromigration, time-dependent dielectric breakdown, and bias-temperature instability accumulating over service life.
The sequence matters: isolate the fault electrically and image non-destructively before anything is opened.
Semiconductor and board defects are rarely isolated to one unit:
Re-energizing a failed board frequently destroys the original defect signature or creates new damage on top of it. Quarantine failed units with their date codes, lot traceability, and any error logs.
By the scale and character of the damage. ESD is a very short, high-voltage, low-energy event that typically punctures gate oxides or fuses the thinnest metallization, leaving small, localized damage that can be invisible until the device fails later. EOS delivers more energy over a longer time and leaves gross thermal evidence — melted bond wires, vaporized metal traces, package discoloration. Under SEM the two produce distinctly different morphologies, and the distinction often decides whether a handling process or a circuit design is responsible.
CAF is a failure inside the laminate rather than on it. Under humidity and an applied bias, copper migrates along the glass-fibre-to-resin interfaces within the board, eventually forming a conductive filament that shorts between adjacent plated holes or traces. It is insidious because nothing is visible on the surface; it takes cross-sectioning or specialized imaging to find. Susceptibility is driven by laminate material, hole-to-hole spacing, drilling quality, and the humidity of the operating environment.
Often yes. Boards that pass bench testing but fail in service usually have a condition that only manifests under real operating stress — a cracked solder joint that opens when hot, a marginal via, moisture-driven leakage, or a latent ESD-damaged device that degrades over time. The approach is to reproduce the operating environment while monitoring, then isolate electrically and image the suspect site. "No fault found" almost always means the test conditions did not match the failure conditions.
Popcorning occurs when a moisture-sensitive plastic package that has absorbed ambient humidity is heated rapidly during soldering. The trapped moisture flashes to steam and cracks or delaminates the package internally, sometimes audibly. The damage may not cause immediate failure, which makes it a classic latent defect appearing as an early field return. It is controlled through moisture-sensitivity-level handling and bake procedures, and it is identifiable by acoustic microscopy.
The failed units, and ideally comparison units from the same and different production lots. Failure analysis on a single unit can establish a mechanism but not its prevalence, and the prevalence question is usually what drives the business decision. Date codes, lot traceability, error logs, and the service and environmental history all materially affect how strong a conclusion can be supported.
Technical briefings from our work in this area.
A part that is not what its marking claims fails in ways the design never anticipated. Detection is a documented sequence, and the supply chain record is half the answer.
readMoisture, ionic contamination and a voltage bias will grow conductive metal between conductors. The board that passed final test genuinely passed it — the short did not exist yet.
readElectrostatic discharge and electrical overstress leave visibly different damage. The distinction usually decides whether responsibility sits with a handling process or a circuit design.
readTell us what you are seeing. We will triage it and connect you with the right expert — usually within one business day.