What is the difference between electrostatic discharge (ESD) and electrical overstress (EOS)?
Electrostatic discharge (ESD) and electrical overstress (EOS) are two different energy regimes: ESD is very short and very high voltage but carries little energy, while EOS delivers more energy over a longer interval — microseconds to seconds — and leaves gross thermal evidence. ESD and EOS are routinely conflated in field reports on failed semiconductor devices, but they are different events with different signatures.
A human-body-model ESD event lasts on the order of nanoseconds. The damage electrostatic discharge produces is correspondingly small and localized: punctured gate oxides, fused thin metallization, damage at the specific structure that happened to be in the discharge path. ESD damage can be invisible at low magnification and, critically, can leave a semiconductor device that still functions.
Electrical overstress leaves melted bond wires, vaporized metal traces, cratered silicon, and discolored or ruptured packages. EOS damage is generally obvious once the package is opened; the analytical work lies in determining what circuit condition produced it.
The field maintains a dedicated body of work on exactly this boundary between ESD and EOS. The annual EOS/ESD Symposium proceedings are the standard reference (EOS/ESD 2018), and a published history of the symposia traces how the distinction between ESD and EOS has been formalized over four decades (EOS/ESD 2015).
Can ESD damage a semiconductor device without making it fail right away?
Yes: an electrostatic discharge (ESD) event can weaken a gate oxide without causing immediate failure, and that latency is the reason ESD attribution matters commercially. The semiconductor device passes final test, passes incoming inspection, is assembled into a product, and fails weeks or months into service as the damaged oxide degrades under normal operating stress.
From the field, a latent ESD failure looks like an early-life reliability problem with the finished product. From the physical evidence, it is a handling event that occurred somewhere upstream — at the component manufacturer, in transit, at a contract assembler, or on the customer line.
Susceptibility to ESD varies enormously by device technology, which is why device-specific characterization work exists — for example, ESD failure-voltage studies on tunneling magnetoresistive heads at drive level (EOS/ESD 2007).
How do failure analysts determine whether a semiconductor failure was caused by ESD or EOS?
Failure analysts determine whether a semiconductor failure was caused by electrostatic discharge (ESD) or electrical overstress (EOS) by working through fault isolation, non-destructive imaging and then decapsulation, in a sequence dictated by the fact that some evidence does not survive opening the package, after which the damage morphology is usually decisive. Fault isolation comes first — thermal emission microscopy, lock-in thermography, and curve tracing to localize the defect electrically while the device is intact. Non-destructive imaging follows: X-ray and acoustic microscopy to find cracks, voids, and delamination inside the package. Only then is the device decapsulated, chemically or by laser, for optical and SEM inspection of metallization and bond wires. Where the failing structure lies deeper, delayering or cross-sectioning reaches it.
At that point the morphology of the damage is usually decisive in distinguishing ESD from EOS. Small, localized oxide puncture with minimal collateral thermal damage points to ESD. Extensive melting along a current path points to EOS. Mixed signatures are common and informative — an EOS event triggered by a circuit condition that a prior ESD-damaged structure created.
Why does it matter whether a semiconductor failure was ESD or EOS?
Whether a semiconductor failure is attributed to electrostatic discharge (ESD) or electrical overstress (EOS) matters because the two point to different owners, and the distinction rarely stays academic. ESD attribution points toward handling and process control, implicating manufacturing and logistics practices and the adequacy of ESD protection programs. EOS attribution points toward the circuit — supply transients, inadequate protection design, a fault condition elsewhere in the system, or an application outside the device rating. In a supplier dispute, in a recall decision, or in litigation over a safety-critical system, those are very different conclusions.
One practical instruction outweighs the rest when a failed board may be examined for ESD or EOS: do not power up the failed board again. Re-energizing frequently destroys the original defect signature or superimposes new damage on it. Quarantine failed units with their date codes, lot traceability, and any stored error logs.
For the full mechanism set and examination protocol, see the Failure Analysis Institute’s specialization area on PCB and semiconductor failure analysis.